Short Resume: [pdf]

Full CV (old): [pdf]

  • 2015-present, Graduate Teaching Assistant, ECE Department, NCSU, Raleigh
    • Assisted for both undergraduate and graduate courses since my induction to the PhD program. ( ECE 109, ECE 506, ECE 463/563, ECE 466/566)
  • 2014-2015, Member Technical Staff, Graphene Semiconductors, Bangalore
    • Worked as on-site STA consultant expert for crucial customers like Sandisk, Lantiq communications (now Intel) and Qualcomm. Activities involved driving timing closure of
      the chips, constraints development and verification and providing CTS strategies for PnR
  • 2011-2014, Design Engineer, Texas Instruments India, Bangalore
    • Worked on 28nm and 40nm technology nodes in various Physical Design and
      Static Timing Analysis roles. Activities: Ownership of the design library for entire SoC team, PnR experiments for various Sub-blocks, Netlist to GDSII flow flush of a crucial test-chip and
      development of timing constraints for various block/top level of the SoCs.