Publications

Lock-free programming and H/W atomics

lfbench: a lock-free microbenchmark suite, International Symposium on Performance Analysis of Systems and Software 2023 [pdf]

(MORE IN WRITING/SUBMISSION PHASE)

Quantum Computing

Automatically Translating Quantum Program from a Subset of Common Gates to an Adiabatic Representation, Reversible Computation 2019 [pdf]

Physical Design and Clock tree synthesis

Clock Tree Synthesis Care-about for Complex SoCs , Design Automation Conference 2012 [pdf]

Placement Aware Clock Gate Cloning and Redistribution Methodology, International Symposium on Quality Electronic Design 2012, TIITC 2011 [pdf]

Clock Tree Considerations for Improved Quality and Robustness, Magma Users Summit on
Integrated Circuits 2011 [pdf]

US Patent:

Placement aware clock gate cloning and fan-out optimization– number: 8,661,374